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Bit
27:16
Name
CH1DATA
Reset
0x000
Access
W
Description
Channel 1 Data
Data written to this register will be written to DATA in DACn_CH1DATA.
15:12
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
11:0
CH0DATA
0x000
W
Channel 0 Data
Data written to this register will be written to DATA in DACn_CH0DATA.
26.5.12 DACn_CAL - Calibration Register
Offset
0x02C
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:23
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
22:16
GAIN
0x40
RW
Gain Calibration Value
This register contains the gain calibration value. This field is set to the production gain calibration value for the 1V25 internal reference
during reset, hence the reset value might differ from device to device. The field is unsigned. Higher values lead to lower DAC results.
15:14
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
13:8
CH1OFFSET
0x00
RW
Channel 1 Offset Calibration Value
This register contains the offset calibration value used with channel 1 conversions. This field is set to the production channel 1 offset
calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
sign-magnitude encoded. Higher values lead to lower DAC results.
7:6
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
5:0
CH0OFFSET
0x00
RW
Channel 0 Offset Calibration Value
This register contains the offset calibration value used with channel 0 conversions. This field is set to the production channel 0 offset
calibration value for the 1V25 internal reference during reset, hence the reset value might differ from device to device. The field is
sign-magnitude encoded. Higher values lead to lower DAC results.
26.5.13 DACn_BIASPROG - Bias Programming Register
Offset
0x030
Reset
Access
Name
Bit Position
Bit
Name
Reset
Access
Description
31:7
Reserved
To ensure compatibility with future devices, always write bits to 0. More information in Section 2.1 (p. 3)
6
HALFBIAS
2011-04-12 - d0001_Rev1.10
1
RW
378
Half Bias Current
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